This invention relates generally to electronic circuits and, and more particularly to providing mixed voltage tolerant input/output electrostatic discharge devices.
Input/output (I/O) devices operate at different voltages. As such, electronic circuitry utilized in I/O devices should be able to operate at different voltages. For instance, I/O devices may be able to operate at 3.3 or 5 volts. Typically, these devices utilize complementary-symmetry metal-oxide-semiconductor (CMOS) technologies and, in particular, utilize field effect transistors (FETs) to drive other circuits and to handle electrostatic discharges (ESD). In some instances, due to availability and space constraints, a 3.3 or 5V FET may not be used. In these instances, stacked or cascoded n-channel field effect transistors (NFETs) are routinely used in mixed-voltage tolerant I/O connections. For instance, a 2.5V stacked NFET (two 2.5 volt serially connected NFET's) is often used for 3.3 or 5V applications if a 3.3 or 5V NFET is not available in the technology or it may be used for cost or area reasons.
Stacked NFETs are essentially two NFETs in series that may be implemented in a single active area with a minimum gate spacing, or they can be implemented in separate active areas. A single active area with minimum gate spacing implementation is preferred due to a smaller resultant device area.
FIG. 1 shows a schematic of a prior art stacked NFET circuit 100. The circuit 100 includes an I/O pad 102. The I/O pad 102 may receive an input from or provide an output to an external device (not shown). The voltage received on the I/O pad 102 may vary. For example, the voltage received on the I/O pad could be 3.3 or 5V. The I/O pad is connected to stacked NFET 104. The stacked NFET 104 includes two NFET's, a first NFET 106 and a second NFET 108. The stacked NFET 104, as is known in the art, functions as both an electrostatic (ESD) device and as a driver circuit. From time to time herein, the first NFET 106 may be referred to as the “top NFET.”
In particular, the second NFET 108, may have its gate coupled to a pre-drive circuit (not shown) to drive an external circuit. In the example shown, the I/O pad 102 is coupled to the drain of the first NFET 106. The source of the first NFET 106 is coupled to the drain of the second NFET 108, the bodies of both the first NFET 106 and the second NFET and the source of the second NFET 108 are coupled together and to ground. The gate of the first NFET 106 is coupled, either directly or through a normally-on PFET, to a supply voltage (VDD) and the gate of the second NFET 108 is coupled to a pre-drive circuit.
FIG. 2 depicts cross-section of the circuit 100 of FIG. 1 as implemented in silicon. The drain pad 102 is coupled to the drain 202 of the first NFET 106. As shown, the first NFET 106 is formed of first drain 202, first gate 204, first source and a body region 208. In more detail, the first drain 202 comprises an N+ region, the first source comprises an N+ region 206, both of which are formed in the P-well body region 208. The first gate 204 is coupled to VDD. The second NFET 108 includes a second drain co-formed with the first source in N+ region 206, a second gate 212, and a second source 210. The second drain and the second source 210 are N+ regions formed in the P-well body region 208. The second source 210 is separated from a p-contact region 214 by a shallow trench isolation region 215. The second source 210 and the p-contact region 214 are coupled to one another and to ground. The entire assembly of FIG. 2 is formed on a P-substrate 216 that serves as a starting material. In this example, the first NFET 106 and second NFET 108 handle ESD and drive an external circuit.
While the circuits described above may work well for their intended purposes, these circuits may have shortcomings. For instance, these circuits may not have tunable ESD trigger voltages, may have on-currents that are too low, or may have gate oxide breakdown issues. Thus, a device that may solve one more of these shortcomings is desired.